In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited onto or removed from a substrate surface. As layers of materials are sequentially deposited onto and removed from the substrate, the uppermost surface of the substrate may become non-planar and require planarization. Planarizing a surface, or “polishing” a surface, is a process whereby material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Compositions and methods for planarizing or polishing the surface of a substrate are well known in the art. Chemical-mechanical planarization, or chemical-mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical composition, known as a CMP composition or more simply as a polishing composition (also referred to as a polishing slurry), for selective removal of material from the substrate. Polishing compositions typically are applied to a substrate by contacting the surface of the substrate with a polishing pad (e.g., polishing cloth or polishing disk) saturated with the polishing composition. The polishing of the substrate typically is further aided by the chemical activity of the polishing composition and/or the mechanical activity of an abrasive suspended in the polishing composition or incorporated into the polishing pad (e.g., fixed abrasive polishing pad).
Cobalt is emerging as a metal for integration into advanced integrated circuit devices. Effective integration of cobalt will require CMP methods with high removal rates, good planarization efficiency, low dishing and erosion, and low defectivity. At pH 9.5 and above, cobalt forms an insoluble, passivating oxide-hydroxide coating. Below that pH, cobalt readily reacts with water to form soluble, hydrated Co(II) species. U.S. Patent Application Publication 2014/0243250 A1 discloses polishing compositions exhibiting moderate cobalt removal rates at pH 9.0 and above, but requires high particle loading and high downforce pressure, which are disadvantageous from economic and processing viewpoints.
Aggressive formulations are normally required to achieve acceptable cobalt rates. Integrated circuit devices typically comprise patterned wafers having circuit lines etched into substrates which typically comprise dielectric materials such as silicon oxide. Layering cobalt over the surface of the patterned substrates allows for formation of cobalt circuit lines. The cobalt is then removed by polishing to the level of the underlying dielectric. Erosion refers to the loss of dielectric materials within the patterned region, and may be mitigated by control of abrasive content. Dishing refers to the loss of cobalt within circuit traces. Dishing control is more challenging and requires polishing compositions with the ability to stop or reduce cobalt removal within the traces once the overlying blanket of cobalt is removed to expose underlying dielectric materials. Recess control refers to dishing control of smaller feature sizes and is encompassed by the term dishing control.
Thus, a need remains in the art for polishing compositions that provide high cobalt removal rates while exhibiting acceptable dishing, erosion, corrosion, and low defectivity.